1. Field of Invention
The present invention relates to an apparatus for receiving moving pictures, and more particularly, to a memory reducing device in an apparatus for receiving moving pictures which is applied to the fields such as a digital television receiver, a digital video conference system and the like.
2. Discussion of the Related Art
As the digital television broadcasting becomes a major issue in that broadcasting field, many efforts have been contributed to compress video data to make a television receiver provide a clear distinction of high definition for watching television at home.
MPEG-2 (moving picture expert group—2) is mainly used for an algorithm to compress the video signals. A compressing ration of the MPEG-2 ranges 1/40 to 1/60 which is a relatively large value.
Algorithms such as MPEG-2 enables to transmit digital data of high definition which are usually difficult to be dealt with through general broadcasting channels and further enables to receive the digital data of high definition at home,
Therefore, the digital television sets used at home require video decoders for MPEG-2 enabling to receive the compressed data and decode into the original video data of high definition.
FIG. 1 shows a block diagram of a MPEG decoding system according to a related art.
Referring to FIG. 1, a transport (TP) decoder 101 selects a program out of a plurality of programs included in a channel and then divide packetized audio and video bit streams. The divided video bit stream is outputted through a data bus to a video decoder 102.
The video decoder 102 gets a pure data information by removing overheads such as various header informations, start code and the like from the inputted video bit streams.
The data information uses variable length decoding (VLD), inverse quantization, inverted discrete cosine transform and motion vectors to achieve the motion compensation. Thus, the video decoder 102 restores the inputted video stream to original pixel values and outputs the restored pixel values to a video display processor (VDP) 103.
The video display processor 103 rearranges and outputs the restored pixel values according to a picture type or outputs the restored pixel values as inputted.
Besides, as mentioned in the above description, a video decoder system taking MPEG-2 as a basic tool uses an external memory 105 comprising a buffer to generally store the bit stream temporarily and at least two frame memories.
DRAMs are used to constitute the frame memories in general. The external memory 105 in the video decoder carries out bit stream write for video decoding, video stream read, data read for motion compensation, decoded data write and data read for display. And, the external memory 105 communicates data with a memory controller 104.
Unfortunately, the external memory 105 in FIG. 1 is proper for processing small data but fails to be proper for processing video data for MPEG-2 MP@HL.
Specifically, large memory capacity and fast transmission speed are required for decoding the video data for MPEG-2 MP@HL. And, bit-buffer size of about 10 Mbits is required for supporting the MP@HL mode for the standard of MPEG-2 and its maximum bit rate amounts to about 80 Mbits/s.
For the above-mentioned reasons, an external memory of about 96 to 128 Mbits using 16 Mbits DRAM as a basis is required for constituting the video decoder for MPEG-2 according to the related art.
Therefore, for securing the cost competition in product and user application, a technology enough to embody excellent image quality as well as reduce the external memory price is strongly required. In view of the trend of providing various OSD (on screen display) functions and services in digital television broadcasting, the capacity of the external memory capacity should be increased in addition.
For instance, in the recent system for restoring the compressed video such as MPEG-2, a variety of services are provided by multi-decoding and displaying many kinds of video signals. In this case, various video signals should be decoded in the memory having a limited capacity.
Considering memory limit, price and bandwidth of a data bus, a memory reducing apparatus for minimizing efficiently the loss of high definition image signals in a video decoding chip is required. And, various methods have been proposed for the solution.
Proposed to eliminate spatial redundancy are memory reducing algorithms built inside the video decoding chip of the related art such as ADPCM (adaptive differential pulse coded modulation) with 50% compression ratio, VQ (vector quantization) with 75% compression ratio and the like. Besides, a compression method that carries out filtering/down-sampling in a DCT frequency range has been proposed as well.
However, the above-proposed methods with 50% to 75% compression ratio have difficulty in providing MPEG-2 MP@HL of high image quality of color components and high textured images. Namely, high definition is inverse proportional to a compression ratio and the relation between the high definition and compression ration needs very complicated algorithm.
Unfortunately, when a memory reduction circuit is embodied as an integrated circuit (IC), it is difficult to implementing the complicated algorithms as well as the number of gates is increased.
As a solution to settle the above problems, an apparatus for receiving moving pictures has been filed to the Korea Intellectual Property Office (Application No. 1999-34694/Application date: Aug. 20, 1999) by the same inventors of the present invention.
The foregoing filed apparatus for receiving moving pictures compresses video decoded data by ADPCM and stores it in an external memory to maintain high definition image as well as carry out motion compensation by macro block unit according to the standard MPEG-2 with ease. And, the foregoing filed apparatus divides the respective macro blocks into 4×8 sub blocks on data compression.
The original pixel value that is not compressed is stored in a first row of each sub block and ADPCM compression is carried out on the rest rows. In this case, data is compressed by applying adaptive standard deviation to quantization and the compressed result is stored in the external memory.